Single Event Effects (SEE) are disturbances in an active semiconductor device caused by a single energetic particle. As semiconductor devices become smaller and smaller, transistor threshold voltages decrease. These lower thresholds reduce the charge per node needed to cause errors. As a result, the semiconductor devices become more and more susceptible to transient upsets.
One type of SEE is a single event upset (SEU). SEU is a radiation-induced error in a semiconductor device caused when charged particles lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs. The electron-hole pairs form a parasitic conduction path, which can cause a false transition on a node. The false transition, or glitch, can propagate through the semiconductor device and may ultimately result in the disturbance of a node containing state information, such as an output of a latch, register, or gate.
One type of SEU is a single event transient (SET). An SET may occur when a particle strikes a sensitive node within a combinational logic circuit. A voltage disturbance produced at that node may propagate through the logic. As a result of the SET, the combinational logic circuit may provide an erroneous output, which could impact the proper operation of a system that includes the circuit.
Typically, an SEU is caused by ionizing radiation components, such as neutrons, protons, and heavy ions. The ionizing radiation components are abundant in space and at commercial flight altitudes. Additionally, an SEU may be caused by alpha particles from the decay of trace concentrations of uranium and thorium present in some integrated circuit packaging. As another example, an SEU may be caused by detonating nuclear weapons. When a nuclear weapon is detonated, intense fluxes of gamma rays, x-rays, and other high energy particles are created, which may cause SEU.
One circuit family used to implement logic functions is termed dynamic logic. In a typical dynamic logic family, clock signals are used to alternate between two modes of operation. These two modes of operation are called the precharge phase and the evaluation phase. The behavior of these two phases is defined by the use of two transistors and clock signals to control current flow within a dynamic logic gate.
In the precharge phase, the clock signal causes one of the two transistors to be conductive, while the other transistor is non-conductive, which allows current to either enter or depart the output node. Typically, the output node is either charged or discharged to one of the power supplies. If the final state of the output node is the high power supply, then the precharge phase is referred to as a precharge high state. Conversely, the precharge phase is called a precharge low state when the final state of the output node is the low power supply (e.g., ground).
In the evaluation phase, the clock signal switches the two transistors from their respective states in the precharge phase to their respective opposing states (i.e., from a conducting state to a non-conducting state, or vice versa). If the dynamic logic component, based on inputs provided to the dynamic logic component during the evaluation phase, permits current flow during the evaluation phase, then the output of the dynamic logic circuit changes from the precharge high or low state to the opposing state. If the dynamic logic component, based on inputs provided to it during the evaluation phase, does not permit current flow, then the output of the dynamic logic circuit does not change from the precharge high or low state.
Since dynamic logic retains the precharge state unless the dynamic logic component is enabled to conduct current during the evaluation phase, dynamic logic offers several advantages. Compared to static logic designs, dynamic logic requires nearly half as many components to implement a given logic function and can offer considerably faster switching speeds. Thus, the benefits of dynamic logic are particularly important to high speed computing, telecommunications, and information networks.
Dynamic logic is also valuable to military and space-based applications, but circuits in such environments may be at risk of SEUs. An SEU can occur in the precharge circuitry or the evaluation circuitry. An SEU in the precharge and/or evaluation circuits may be sufficient to cause an erroneous result in a circuit using dynamic logic.
Therefore, it would be beneficial to harden dynamic logic circuits against SEU.